Corrected input for prim/sec phase shift of VariableSquareWave_PhaseShift block, to comply equation (2) from paper "Overview of CLLC Modulation Strategy".

Added new modulator implemented in Plecs using C-Script CLLC/Plecs/CLLC_Plecs_PFM_PSM2.slx (from "C_Code PWM PLECS" block from var_PWM_Testmodel model from multi_pwm project).

Added Plecs_PFM_PSM_combine.slx to learn, how we can combine the Variable Frequency PWM and the Variable Phase PWM block in Plecs to one block

Created VariableSquareWave_PhaseShift3 block, with single output for each leg. The inverting is done outside the block.

Von hier: https://www.radiolocman.com/review/article.html?di=642905 das Schaltmuster für 3L flying cap buck converter nachvollzogen, mit Matthias überprüft. Für den boost converter dann einfach Ein- und Ausgang vertauscht (also auch Quelle und Last vertauscht).

Added ThreeL_FlyingCap_buck.slx and ThreeL_FlyingCap_boost.slx models. They can be used as basis to model the LEITNING DC/DC boost converter.

Added VariableSquareWave_PhaseShift2 Block with modulation from Jonas project BiDiLa, which uses mod functions. This blocks contains primary side, secondary side and prim-sec side phase shift inputs + frequency input.

Added modulation from Jonas project BiDiLa. This modulator was implemented using mod functions instead of sin and arcsin. The carrier signal is a triangle between 0 and 1. My carrier signal starts counting up beginning with 0.5, Jonas's starts counting down beginning with 1. So, my carrier signal is delayed by a quarter period compared to Jonas' carrier signal.

Modified VariableSquareWave block in Plecs model of CLLC_Plecs_PFM_PSM.slx, to include PS, SS and PS phase shift

Added CLLC/Plecs/CLLC_Plecs_Modulator_JS.slx from Jonas from the Project BiDiLa (model V006_SimModel_MCT.slx)

Wrote first sketch of ideas how to derive the gain response of the CLLC resonant converter as a function of the switching frequency and a primary side phase shift, see CLLC/TransferFunc/CLLC_TF_Doku.

Added CLLC/Plecs/CLLC_Plecs_PFM.slx and CLLC/Plecs/CLLC_Plecs_PFM_PSM.slx. Build a variable square wave generator with frequency control and phase shift for the primary side bridge.

Added CLLC/Plecs/CLLC_Plecs_PFM.slx and CLLC/Plecs/CLLC_Plecs_PFM_PSM.slx. Build a variable square wave generator with frequency control and phase shift for the primary side bridge.

CLLC/TransferFunc/CLLC_TF_PFM_plot.m
CLLC/TransferFunc/CLLC_TF_PFM_PSM_plot.m
CLLC/TransferFunc/CLLC_TF_plot_wrong1.m
CLLC/TransferFunc/CLLC_TF_plot_wrong2.m

to include the parameter definitions inside the script

Updated 2 scripts CLLC/TransferFunc/CLLC_TF_PFM_plot.m and CLLC/TransferFunc/CLLC_TF_PFM_PSM_plot.m, all parameters from Daniels Plecs model are now defined in the scripts

Added script for calculating output voltage of CLLC converter using PFM and PSM method, using equations from paper "Overview of CLLC Modulation Strategy"

When using the LV bridge as passive rectifier (only diodes), the output voltage is equal to the gain (transfer function) times the input voltage.

If the LV Bridge is used as an active rectifier, then the MOSFETs switch later than the diodes conduct, which is why the average current in the output capacitor is not zero and the output voltage drops.

Added phase shift on HV side MOSFETs, so the LV side MOSFETS switches at the same moments, as Diodes, to compensate for the voltage drop on the output

Active switching (MOSFETs) on the LV results in a lower output voltage, than is defined by the CLLC transfer function. The output voltage is only correct when conducting passively (Diodes).

Created CLLC_Plecs.slx model to confirm H_abs transfer function value in the resonance point fr1, there it gives the correct simulation result. As soon as I move a small delta out of the resonance point, the output voltage approaches zero.